Analog-to-digital converters (ADC's) translate an analog voltage or current input signal into a digital representation of that signal. Some ADC architectures include a digital-to-analog converter (DAC), which is a circuit that receives a digital input and, in response, produces a voltage or current that corresponds to an input.
A common type of ADC is known as a successive-approximation ADC. A successive-approximation ADC includes a DAC, a comparator, and a successive-approximation register (SAR). Successive-approximation converters apply a binary search algorithm to determine the closest digital word to match an input signal. Specifically, in the first period, after possibly the reset period, the MSB, is determined. In the second period, the next bit is determined, and so on until all N bits are determined.
Another type of ADC is the charge redistribution (or charge balance) ADC. Generally, this sort of converter operates by first trapping a quantity of charge related to a voltage to be measured in one or more sampling capacitors, and then determining the amount of trapped charge using charge scaling on a capacitive ladder circuit. The ladder circuit typically includes a series of binary-weighted capacitors that each have a common plate connected to the sampling capacitor, with each capacitor in the ladder corresponding to a single bit of the converter. The smallest ladder capacitor corresponds to the least significant bit (LSB) of the converter, and the remaining capacitors are each twice as large as the last, with the largest one corresponding to the most significant bit (MSB) of the converter.
To determine the amount of charge trapped in the sampling capacitor, and hence the value of the voltage to be measured, charge redistribution converters have a SAR to switch the ladder capacitors one at a time between ground and a precise voltage reference. Each time the converter switches a ladder capacitor, the sampling capacitor and the ladder form different capacitive voltage dividers between ground and the reference voltage, and the converter tests the output of each dividers with a comparator. Depending on the result of the test, the converter leaves the tested capacitor connected either to the reference or to ground, and sets its corresponding bit to either a one or a zero. Once the converter has tested every ladder capacitor, it can provide the weighted sum of all of the corresponding bits on a digital output as a measure of the voltage.
FIG. 1 illustrates an example of a successive-approximation ADC that uses a voltage-scaling and charge-scaling charge redistribution DAC. Because this DAC uses a resistor string for voltage-scaling it is also called a resistor DAC (RDAC). In this example prior art ADC, charge scaling with a capacitor ladder to determine the most significant bits is combined with voltage scaling with a resistor ladder to determine the least significant bits.
The servo system of a computer disk drive includes a servo demodulator and an ADC. The servo system receives servo burst signals from certain transducer heads and uses those signals to determine the radial position of the heads on the disk. The disk drive microprocessor can determine the position of the heads in response to the integral of the servo burst over a certain time period. The ADC, which is typically eight to 10 bits wide, converts the integral to a digital value and provides it to the microprocessor. In certain servo systems, the servo demodulator estimates this integral by full-wave rectifying the servo burst, detecting the peaks, and estimating the integral based on an assumption that the waveform is known. In other servo systems, the servo demodulator determines the integral by full-wave rectifying the servo burst and providing the rectified signal to an analog integrator circuit. The latter type of servo demodulator is more accurate and is known as an area integrating servo demodulator (AISD). The AISD is conventionally implemented with analog components in a BiCMOS integrated circuit or chip.